QCA Implementation of Arithmetic Unit using Reversible Logic Gates

In the dynamic landscape of VLSI technology, Quantum-dot Cellular Automata (QCA) has emerged as a promising contender to traditional CMOS technology, owing to its potential for smaller feature sizes, higher operational frequencies, and reduced power requirements. Early investigations in the QCA realm have predominantly emphasized the deployment of varied sequential and combinational circuit models, acting as fundamental elements for numerous applications. However, recent trends have seen a shift towards the development of application-specific designs using QCA. Motivated by this trend, this paper endeavors to explore the utilization of reversible logic gates in the design of an Arithmetic Unit within the QCA framework. The objective is to implement key arithmetic components, including a Full Adder, Full Subtractor, Multiplier, Divider, and then integrate them using a 4:1 MUX to form a comprehensive Arithmetic Unit. The performance evaluation of these components is conducted across multiple metrics, including area utilization, quantum cost, delay, energy consumption, and QCA cell utilization. To confirm the functionality of the proposed designs, comprehensive simulations are performed, generating waveform outputs that undergo thorough functional verification.