CMOS-Compatible Single-Gated Memtransistor Having 3-D Bulk Channel Embedded with Quantum Well Memory Nodes for Fast Training of Deep Neural Network

Recently, three-terminal synaptic devices having gate, source, and drain electrodes have been actively researched to compensate for the poor reliability of two-terminal synaptic devices such as resistive random access memory (ReRAM) and phase change random access memory (PCRAM) 1 . Two-terminal devices inherently suffer from read disturbance problems, where the stored resistance state changes gradually during the read process of the artificial neural network 2 . In addition, two-terminal devices essentially require selection devices for performing the write (program or erase) and read process, which is limited to commercialization because matching of the electrical characteristics between the selection device and the synaptic device was extremely difficult 3 . Moreover, the training speed of artificial neural networks would degrade due to the constant on/off ratio of conductance of two-terminal synaptic devices. To solve this problem, the memtransistors that can change the conductance range of the channel with gate bias have been reported. However, most of the reported memtransistors employed 2-D materials such as MoS 2 , WSe 2 , and SnS 2 as a channel layer, which is a limitation for uniform large-area thin film growth 4–6 . In other words, the memtransistors with a 2-D channel layer do not have CMOS compatibility. In this study, for the first time, we designed a CMOS-compatible single-gated memtransistor having an indium-gallium-zinc-oxide (IGZO) channel embedded with quantum well memory nodes via Au nanoparticles. The quantum well memory nodes were obtained by precisely designing the diameter of Au nanoparticles in the IGZO 3-D bulk channel and SiO 2 gate oxide interfaces. In addition, the quantum well memory nodes using Au nanoparticles were investigated by an energy band diagram obtained from ultraviolet photoelectron spectroscopy (UPS) analysis of Au, IGZO, and Al source/drain electrodes. Thereby, the gate-tunable pinched hysteresis loops in the output curve of the designed memtransistor were achieved ranging from -30 to 30 V, which present channel conductance tuning by controlling the amplitude of gate bias. In addition, the gate-tunable synaptic plasticities (i.e., long-term potentiation (LTP) and long-term depression (LTD)) were obtained by changing the amplitude of gate bias from 10.0 to 13.5 V at an incremental of 0.5 V, exhibiting exponential growth of maximum channel conductance depending on the amplitude of gate bias. Finally, we demonstrated the fast training of the hardware-based deep neural network simulation using the gate-tunable synaptic plasticity of the designed memtransistor. The mechanism of single-gated memtransistor having quantum well memory nodes via Au nanoparticles and its application will be presented in detail. Acknowledgement This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (No. RS-2023-00260527) and Institute of Information & communications Technology Planning & Evaluation (IITP) under the artificial intelligence semiconductor support program to nurture the best talents (IITP-(2023)-RS-2023-00253914) grant funded by the Korea government(MSIT)" References Fuller, E. J. et al. Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing. Science (80-. ). 364 , 570–574 (2019). Yoon, J., Chang, M. & Khwa, W. Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. Jssc 57 , 1–13 (2022). Kim, H. J. et al. Super-Linear-Threshold-Switching Selector with Multiple Jar-Shaped Cu-Filaments in the Amorphous Ge3Se7 Resistive Switching Layer in a Cross-Point Synaptic Memristor Array. Adv. Mater. 2203643 , (2022). Lee, H. S. et al. Dual-Gated MoS2 Memtransistor Crossbar Array. Adv. Funct. Mater. 30 , 1–12 (2020). Ding, G. et al. Reconfigurable 2D WSe2-Based Memtransistor for Mimicking Homosynaptic and Heterosynaptic Plasticity. Small 17 , 1–13 (2021). Rehman, S., Khan, M. F., Kim, H. D. & Kim, S. Analog–digital hybrid computing with SnS2 memtransistor for low-powered sensor fusion. Nat. Commun. 13 , 1–8 (2022). Figure 1