Hard entropy limits of impurity doping prevent further miniaturization of low nanoscale silicon-based very large scale integration (VLSI) devices, thereby obstructing the path toward more energy-efficient VLSI designs with higher yield in compute power. As demonstrated here by synchrotron UV photoelectron spectroscopy (UPS) and X-ray absorption spectroscopy in total fluorescence yield mode (XAS-TFY), intrinsic Si at the bottom of the nanoscale (i-nano-Si) turns into strong p- or n-Si by embedding in silicon nitride (Si3N4) or silicon dioxide (SiO2), respectively. The associated Nanoscale Electronic Structure Shift Induced by Anions at Surfaces (NESSIAS) creates a p/n junction in i-nano-Si by the quantum-chemical impact of Si3N4- vs SiO2-coating, providing energy landscapes to accumulate electrons (holes) when SiO2- (Si3N4-) coated, with free charge carriers provided by metallic interconnects. Hybrid density functional theory (h-DFT) calculations demonstrate Si NWire FETs with physical gate lengths down to 3 nm, while the electronic structure remains stable under carrier injection. A mesoscopic band model derived from synchrotron characterization data on ultrathin embedded Si nanowells (NWells), and from h-DFT confirms and further explains the NESSIAS impact to generate p/n homojunctions in i-nano-Si. Presenting a paradigm shift for Si-based VLSI, NESSIAS removes miniaturization limits, achieves faster charge carrier transport with massive reductions of energy demand and associated heat generation as required for ultralow power VLSI, and enables full cryo-functionality for quantum computing.
König et al. (Wed,) studied this question.