This paper presents a high-throughput, low-latency image processing architecture implemented on FPGA using parallel VLSI pipelines. The design integrates core image processing functions—convolution, Sobel-based edge detection, histogram equalization, and adaptive thresholding—into modular, deeply pipelined hardware units. Each module is optimized for energy-efficient computation and real-time throughput using shared memory buffers, fixed-point arithmetic, and clock gating techniques. The system leverages the reconfigurability of FPGAs to achieve pixel-level parallelism, enabling one output per clock cycle after pipeline initiation. Implemented on a Xilinx Kintex-7 FPGA, the architecture achieves up to 180 frames per second (fps) processing speed for 256×256 grayscale images while maintaining low power consumption across all modules. Experimental results demonstrate that the proposed framework provides substantial performance gains over software implementations and is highly suitable for deployment in embedded vision systems, surveillance platforms, and mobile imaging devices. The scalable and reconfigurable nature of the design further enables integration into complex image analysis pipelines.
Rao et al. (Thu,) studied this question.