Timing closure is a critical but effort-taking task in VLSI designs. In this paper, we investigate timing models and their associated optimization techniques suitable for integration into early design process. For accurate timing analysis at placement stage, an innovative timing prediction model that can be transformed into a derivable function is proposed, serving as a replacement for the conventional Elmore delay. One significant advantage of derivable timing models is their ability to be formulated as mathematical functions. This enables the derivation of gradients, which can be explored as direct timing optimization guidance during design process. Therefore, we further present a timing optimization method through model integration into iterative placement process. Experimental results demonstrate that our derivable timing model provides accurate prediction performance. Additionally, when integrated into the placement stage, it outperforms the use of Elmore delay and non-derivable models, achieving 12% ∼ 24% smaller Total Negative Slack (TNS) and Worst Negative Slack (WNS), with an average wirelength reduction of 1% ∼ 5%.
He et al. (Mon,) studied this question.