VLSI floorplanning is a fundamental step in physical design automation that directly impacts chip performance, power consumption, and area utilization. Classic optimization methods include SA, DMT, and PSO; their convergence speeds are rather poor, especially for large-scale designs. This paper addresses both 2D and 3D floorplanning using a Genetic Algorithm (GA). GA represents the floorplans as chromosomes and applies selection, crossover, and mutation to improve block placement iteratively. Experimental comparisons, presented in a two-row tabular format, show that the GA achieves higher efficiency in block placement, wirelength reduction, and computation time compared to SA, DMT, and PSO. The results confirm that GA is indeed one of the effective solutions for large-scale floor planning problems.
Prabu et al. (Thu,) studied this question.