ABSTRACT Triangle counting (TC) is a fundamental operation in graph computing. However, conventional TC algorithms based on binary matrix operations suffer from low computational efficiency due to high storage‐to‐computation ratios and irregular memory access patterns, both exacerbated by the bandwidth bottleneck of the von Neumann architecture. To overcome these limitations, this paper presents a binary vector‐matrix multiplication circuit based on in‐memory computing, specifically designed to accelerate TC algorithms. The intersection‐based TC approach is first reformulated as a constrained binary matrix multiplication problem, enabling the design of a programmable in‐memory computing circuit. By modulating the gate voltage of CMOS transistors, the circuit efficiently manages constraints to accelerate vector‐matrix operations. Building on this foundation, a hardware acceleration scheme leveraging block partitioning and parallel computing is proposed. PSPICE simulation results demonstrate an average computational accuracy exceeding 99% across various matrix sizes and robustness against noise, maintaining over 95% accuracy under 10% voltage variation. Compared to traditional digital processors, the proposed solution achieves a speedup of approximately three orders of magnitude (1000).
Du et al. (Tue,) studied this question.
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