Neuron Smart Inference (NSI): Coordinate-Aware LLM Execution on Consumer Hardware

Description Execution Framework for Geometry‑Native LLM Inference Neuron Smart Inference (NSI) is the execution layer of the NSI Core Series. It assembles the three foundational mechanisms introduced in earlier papers—Spherical Grid Storage (SGS), Axis‑Aware Layouts, and Frozen Onion—into a coherent, production‑ready runtime for large language model inference on consumer hardware. NSI treats LLM inference as a spatio‑temporal data problem rather than a random‑access memory problem, enabling models far larger than VRAM to execute efficiently by aligning storage layout with the natural geometry of LLM access patterns. The NSI Container functions as a coordinate‑aware storage runtime: a transparent translation layer that maps logical (r, θ, φ) coordinates to physical NVMe addresses without requiring any modifications to inference engines such as llama. cpp, ollama, or vLLM. Through non‑invasive acceleration, zero‑copy temporal semantics, and adaptive mapper switching, NSI enables geometry‑native execution on commodity hardware. Synthetic benchmarking across four LLM workload patterns validates a two‑mapper architecture—LayerMajor/linear for standard inference and LayerMajor/logR for long‑context bimodal access—while mapperₕistory ensures coherence across layout transitions without data movement. This work is part of the NSI Core Series, providing the execution framework that integrates coordinates, layouts, and temporal semantics into a unified system for practical deployment. Abstract Neuron Smart Inference (NSI) is a coordinate‑aware execution framework for large language models that assumes models exceed VRAM capacity. In this regime, inference bottlenecks shift from computation to memory orchestration: how data is laid out, how temporal evolution is handled, and how storage tiers are navigated. NSI assembles three mechanisms into a unified runtime: (1) Spherical Grid Storage (SGS) provides the (r, θ, φ) coordinate system; (2) Axis‑Aware Layouts define traversal strategies optimized for layer‑sequential access; (3) Frozen Onion introduces temporal reference frames and mapperₕistory for zero‑copy aging and layout switching. The NSI Container exposes a standard file interface to inference engines while internally translating byte offsets into geometric coordinates and optimized NVMe accesses. Synthetic benchmarking validates a two‑mapper architecture: LayerMajor/linear dominates standard inference (mean jump 1, 007 vs 23, 697 for Hilbert), while LayerMajor/logR dominates long‑context bimodal access (mean jump 1, 486 vs 87, 067 for linear). WorkloadDetector triggers mapper transitions, and mapperₕistory preserves read coherence without data movement. Analytical projections show 6, 000× theoretical and 500–2, 000× realistic speedups over flush‑on‑switch strategies. NSI provides a practical, production‑ready execution layer for geometry‑native LLM inference, enabling large‑model deployment on consumer hardware through coordinate‑aware storage, zero‑copy temporal semantics, and adaptive traversal strategies. Background This work is the fourth entry in the NSI Core Series, assembling the mechanisms defined in earlier papers into a complete execution framework: Spherical Grid Storage (SGS) — 10. 5281/zenodo. 18665189 Axis‑Aware Layouts — 10. 5281/zenodo. 18665191 Frozen Onion: Temporal Reference Frames for Zero‑Copy Memory Systems — 10. 5281/zenodo. 18665193 Neuron Smart Inference (NSI) — 10. 5281/zenodo. 18665206 Spatially‑Aware NVMe Devices for AI Workloads — 10. 5281/zenodo. 18665227 Methodological foundations are documented in: Intuitive‑Theoretic Synthesis (ITS) — 10. 5281/zenodo. 17633100 The Practice of Human‑AI Synthesis — 10. 5281/zenodo. 17763521 The Minimal Knowledge Paradox — 10. 5281/zenodo. 17931472 Design as Epistemological Pathway — 10. 5281/zenodo. 18067554 Key Contributions NSI Container: a coordinate‑aware storage runtime for LLM inference Non‑invasive acceleration layer compatible with existing inference frameworks Two‑mapper architecture (LayerMajor/linear + LayerMajor/logR) validated across four LLM access patterns WorkloadDetector for automatic mapper switching based on access geometry Integration of Frozen Onion for zero‑copy aging and layout coherence Multi‑session architecture with shared weights and isolated KV caches FUSE‑based deployment for universal compatibility and transparent operation Research Impact This work contributes to AI systems engineering, storage architecture, and inference optimization by: Demonstrating geometry‑native execution for models larger than VRAM Providing a practical runtime for coordinate‑aware storage on consumer hardware Enabling adaptive layout switching without data migration Reducing NVMe random‑access penalties through axis‑aware traversal Offering a generalizable execution model for future spatio‑temporal AI workloads Establishing a new class of storage runtime analogous to MMUs, hypervisors, and RAID controllers Access and Documentation ORCID: https: //orcid. org/0009-0003-4876-9273 Academia. edu: https: //independent. academia. edu/MarceloTeixeira214 LinkedIn: https: //www. linkedin. com/in/marcelo-emanuel-paradela-teixeira-702082382/ Email: marcelo. soul. ai@gmail. com License: CC BY-NC 4. 0 © Marcelo Emanuel Paradela Teixeira 2026