Design of Novel 64- bit Multiplier-Accumulator using Vedic Multiplier & Hybrid Adder

Multiplication and accumulation form the core of numerous digital applications, including image processing, AI inference, and embedded system operations. This paper presents a 64-bit multiplier-accumulator (MAC) architecture that incorporates the Urdhva Tiryagbhyam method from Vedic mathematics for fast and efficient multiplication. The proposed design leverages a hybrid adder architecture, combining Carry Skip Adder (CSKA) and Ripple Carry Adder (RCA), to achieve a balance between speed, power efficiency, and chip area. Implemented in Verilog HDL and synthesized using Xilinx Vivado, the proposed unit exhibits significant enhancements in delay, area, and power consumption when compared with conventional approaches.