Multiplication is a fundamental mathematical operation that finds extensive applications across various disciplines, particularly in computation-intensive and error-resilient applications, such as image processing. As hardware circuits become more complex, there is a growing demand for approximation circuit methods. Implementation of approximate multipliers has the potential to yield substantial reductions in hardware costs while maintaining acceptable performance levels. Most current designs for approximate multipliers are optimized for ASIC-based circuits, which may not produce similar performance improvements when adapted for FPGA-based circuits. Additionally, many of these existing multiplier designs are limited to unsigned numbers. This paper proposes a novel approach for designing signed approximate multipliers tailored specifically for FPGAs. Two efficient architectures are introduced that efficiently utilize key FPGA components, such as LUTs and Carry4 primitives, by designing the optimal LUT-Carry4 netlists. A Pareto-based analysis is also performed to balance trade-offs and achieve a low mean error distance (MED). Simulation results confirm that the proposed architectures offer superior performance compared to existing signed approximate multipliers, delivering improved power efficiency, reduced resource usage, shorter critical path delay (CPD), and enhanced computational accuracy. The practical applicability of these approximate multipliers is further validated through their use in image processing applications.
Hassan et al. (Sat,) studied this question.