Abstract As a forward-looking theoretical hypothesis, this study addresses the three core pain points of chips in the post-Moore era: the physical limit of two-dimensional integration, power consumption wall, and low interconnection efficiency, as well as the difficulty in meeting the differentiated needs of CPU, GPU, and AI chips through a single architecture. Breaking away from the inertial thinking of the semiconductor industry, it proposes an innovative concept of multi-chip integration inspired by the mechanical properties of mortise and tenon in traditional Chinese architecture (such as brackets in the Forbidden City and components of the Yingxian Wooden Pagoda). The core is to migrate the wisdom of "modular interlocking and force-thermal synergistic conduction" in traditional Chinese architecture to the micro-design of 1-10μm chips, constructing a four-dimensional collaborative architecture of "3D interlocking - multi-element synergy - function integration - scenario adaptation". By designing diversified mortise and tenon interconnection structures, three-layer three-dimensional computing units, function-oriented multi-material systems (compatible with silicon-based and non-silicon materials), vascularized heat dissipation networks, and standardized reconfigurable modules, customized adaptation of multi-chips is achieved. Based on the theoretical deduction of geometric topology and heat transfer, and cross-validation with 32 authoritative literatures, the number of interconnection nodes in this architecture is doubled compared with traditional 3D integration (interconnection freedom expanded from 3 directions to 6 directions). The theoretical computing power density of CPU/GPU/AI chips reaches 3 times, 4 times, and 3.5 times that of 28nm planar chips respectively, and the R Application Date: 2025.12.10; PCT application is planned to be filed within 12 months), with highly consistent core theoretical logic. Update 1: This is Not Merely a Hypothesis, but the Future (Beijing Time 15:22, March 4, 2026) Paper Version: V2.0 (Update Note: Only the author profile, data update and academic interaction statement have been updated; the core content of the paper remains unchanged.) I once thought this paper, along with my work on brain-computer interfaces, would gain little traction for being too cutting-edge and groundbreaking—mere hypotheses in the eyes of many. However, as Zenodo finalized the download statistics over the past two days, I noticed this paper’s download figures are far from single-digit: with 21 views and 47 downloads, the download count is more than double the view count. This makes me realize that this research is highly valued and appreciated by scholars in academia and the semiconductor industry alike. I want to clarify that this paper marks my debut academic work—it signifies the start of my journey as an independent researcher, and also the genesis of my explorations into dynamic systems, game theory, communication theory, food science, cosmology, and potentially more fields in the future. The discipline of Trait Lock Theory was formally distilled from my third paper on dynamic systems; thus, starting from my fourth work, I have essentially mastered the key to conducting research across any domain. Its embryonic form is palpable in this paper: the reverse migration of the mechanical structure of mortise and tenon joints to the microcosmic field of semiconductors itself embodies the core philosophy of my Trait Lock Theory—penetrating superficial manifestations to reach the intrinsic essence. Though this discipline had not yet been formally established when I wrote this paper, its ideological prototype is still discernible. With this understanding, I wish to be forthright: from the title of this paper, can you sense that it is the first installment of the Mortise and Tenon Full Stack series? In fact, I have already completed the second (Performance Volume) and third (Instruction Set-level Volume) installments. Taking traditional 28nm chips as the benchmark, the theoretical performance of my mortise and tenon structured chips can achieve a 192x performance boost. Why is this figure so staggering? Because my chip, with its 3D stereoscopic structure, achieves an intrinsic performance improvement through multiplication, in stark contrast to the additive performance gains of planar chips. Fundamentally, my chip adopts 16-bit as the benchmark number system—this alone delivers a 4x performance improvement over the traditional binary system, not to mention enhancements in other aspects. Moreover, this performance gain only refers to improvements at the physical or hardware level, with software-based boosts such as turbo boost not yet factored in. Thus, the 192x performance improvement can be understood as a side-effect-free native performance enhancement. To put it in perspective in terms of equivalent quantity, my 28nm mortise and tenon structured chip is equivalent to 41.8 current 3nm process chips. This is the disruptive nature of my mortise and tenon architecture: it does not merely optimize existing manufacturing processes, but completely restructures the underlying logic of performance generation. Traditional chips have reached the end of the road in planar manufacturing, and my mortise and tenon chip has already outperformed all current chips even in its theoretical form. Even accounting for various losses in manufacturing and production, a practical performance boost of at least 150-160x can still be guaranteed upon commercialization. And what if more advanced processes such as 14nm, 7nm, 5nm, or 3nm are adopted? Therefore, my statement that the mortise and tenon chip is the unrivaled optimal path for future 3D structured chips is no exaggeration, but a plain fact. The mature application and engineering validation of the mortise and tenon structure in ancient Chinese architecture span more than 3,000 years; its mechanical logic has stood the test of thousands of years of practice, proving to be stable and reliable, and there is practically no structural design that can surpass it. As for why the second installment has not been published: I intend to release it only after research teams or corporate research institutes collaborate with me to create a feasible prototype chip. It is necessary to develop the first viable chip based on the 28nm process before publishing the second paper—otherwise, the publication would be meaningless. Here, I simply aim to demonstrate the immense performance potential of my chip. Once the 28nm prototype chip is completed, we can proceed to tackle more advanced manufacturing processes such as 14nm, 7nm and 5nm. It is also worth noting that the success of a 28nm prototype would render all current traditional chips—including those produced by Intel, AMD, ARM, and Apple’s M1 series—no match for my mortise and tenon chip. If you, or any interested enterprises and research institutes, aspire to shape the future, my mortise and tenon chip is an exceptional direction to pursue. At the very least, it represents a new architecture with a foreseeable and quantifiable theoretical performance— a rising sun and a beacon of hope, in contrast to the stagnant traditional chip industry that has hit its technological ceiling. Investing in the entirely new field of mortise and tenon chips is far more valuable than pouring resources into the traditional chip industry, where only marginal performance improvements are possible. This is the optimal and future-oriented path forward. The second installment (Performance Volume) will only be published upon the completion of the prototype chip, and its release will bring a qualitative surge in the stock price or valuation of the team or enterprise that develops the prototype. I am a pragmatic researcher who values real-world implementation, and every paper I publish is a high-value academic achievement. Even if my foundational theories do not receive immediate attention due to their profundity, time will prove their worth. Furthermore, I will also write applied research papers to popularize these theories. If you are interested in mortise and tenon chips, I welcome your contact—my email address has always been publicly available. Even if no one reaches out, it is of little consequence to me: the semiconductor field is just a small part of my research scope, while for those working in it, it is the future. I am an originator of 0-to-1 theoretical frameworks, and my research is driven by curiosity. There are numerous more intriguing fields awaiting my exploration. Ultimately, the commercialization of the mortise and tenon chip does not depend on me, but on you—enterprises, research institutes, and teams with the vision and resolve to innovate.
Relike Zhou (Wed,) studied this question.