What question did this study set out to answer?

The aim is to develop a state-aware ternary logic architecture using existing MOSFET technology.

April 6, 2026Open Access

MOSFET-Based State-Aware Ternary Logic Architecture

Key Points

The aim is to develop a state-aware ternary logic architecture using existing MOSFET technology.
Introduced a double-floor logic interpretation combining voltage regions with an internal state variable.
Defined two operational floors to represent ternary states through overlapping logical values.
Utilized circuit-level design and SPICE-based simulations to validate the concept.
Demonstrated feasibility of the architecture through simulations.
Showed potential for using conventional MOSFETs to implement a ternary logic system.

Abstract

This paper presents a state-aware ternary logic architecture implemented using conventional MOSFET primitives. Rather than proposing a new physical ternary transistor, the work introduces a double-floor ("double-decker") logical interpretation in which binary-reliable voltage regions are combined with an internal state variable to emulate ternary behavior. The architecture defines two operational floors that share an overlapping logical value and employs floor transitions, comparators, and voltage mapping to represent ternary states 0, 1, 2. A circuit-level design and SPICE-based simulation framework are described to demonstrate feasibility. This work is intended as a Version 1 conceptual foundation for continued research into state-based multi-valued logic architectures.

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