The rapid growth of the Internet of Things (IoT) is fundamentally altering industrial and economic landscapes by embedding smart, connected devices into everyday operations. Despite these benefits, significant concerns regarding data protection and user privacy continue to obstruct the widespread use of these technologies, particularly with the looming threat of quantum computing. Implementing post-quantum cryptographic (PQC) solutions is vital for addressing these risks, yet the limited resources found in IoT edge devices present major deployment challenges. Lattice-based cryptography has become a leading solution to these problems, largely because it depends on efficient polynomial multiplication. Enhancing the execution of this mathematical operation is crucial for improving the overall performance of PQC protocols. In this work, we introduce a hybrid serial–parallel systolic architecture specifically engineered for polynomial multiplication within the Binary Ring Learning With Errors (BRLWE) scheme. Designed for the security processors used in IoT hardware, this architecture significantly increases processing speeds while minimizing the use of hardware resources and reducing energy consumption. Such improvements are critical for establishing a secure IoT infrastructure that is resilient against quantum-era attacks and capable of supporting industrial expansion. Moreover, this research aligns with global Sustainable Development Goals (SDGs) 8 and 9 by building trust in innovative systems and fostering a more secure, sustainable, and productive digital economy.
Ibrahim et al. (Fri,) studied this question.
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