In this paper, we propose a new synthesis method for LUT-based Moore finite state machines (FSMs) with twofold state assignment (TSA). The method introduces an additional core of partial input memory functions (IMFs), resulting in an architecture with two IMF cores. The first core is based on structural decomposition using additional partial state variables, whereas the second uses maximum binary state codes. Both cores are implemented as single-level circuits. We formulate the conditions under which the proposed method can be applied and show that it improves both the area and timing characteristics of the resulting FSM circuits. The method exploits pseudoequivalent state classes to reduce the number of literals in sum-of-products describing partial IMFs. The developed FSM architecture is organized into three logic stages. At the first stage, two dedicated blocks generate partial IMFs. At the next stage, these intermediate functions are merged and used to form the maximum binary state code. The final stage produces both the output signals and the partial state encoding. The proposed method is illustrated by a synthesis example and validated using standard benchmark FSMs. The obtained results indicate that the method is particularly suitable for larger and more complex Moore FSM implementations.
Barkalov et al. (Sat,) studied this question.