Heuristic optimization of multiplierless decimation filter for multi-standard wireless applications

Most communication is now done in the digital realm due to the advancement of more potent and compact techniques for creating digital circuitry on silicon chips. This work introduces an efficient approach for developing a reconfigurable multiplier-less decimation filter, which is appropriate for multi-standard wireless applications. The proposed work utilizes cascaded integrator comb (CIC), polyphase and half-band filters, designed with the assistance of high-speed adders. Endeavoring to enhance passband and stopband performance, a unique polynomial function is used to design the filter, which shows better results than the existing work. Ultimately, these filter structures are integrated with a control switch to create the proposed decimation filter, making it well-suited for multi-standard wireless applications, including IEEE 802.11g/n/ac/ax. The decimation filter has been built on Xilinx Kintex 7 Field Programmable Gate Array, and utilization of LUTs, power consumption and delay are examined. Based on the attained results, the proposed decimation filter with HCA shows a 46.38% minimization in LUTs, a 36.93% reduction in path delay and an 85.39% drop in power consumption than the previous work. Moreover, the input and output spectrum of all four IEEE 802.11 applications are analyzed using MATLAB.