What question did this study set out to answer?

The aim is to design and verify a RV32I compliant RISC-V processor core for educational and prototyping purposes.

May 13, 2026Open Access

Architectural Implementation and Cycle-Accurate Functional Verification of an RV32I RISC-V Processor Core for High-Reliability Logic Design

Key Points

The aim is to design and verify a RV32I compliant RISC-V processor core for educational and prototyping purposes.
Architectural design and implementation in Verilog HDL of a single-cycle processor core.
Cycle-accurate functional verification using a Fibonacci benchmark program on Xilinx Vivado.
Automation flow with TCL for state dumps and waveform analysis to ensure functional correctness.
Demonstrated correct instruction execution with no errors during simulation.
Confirmed stable control flow and reliable memory operations throughout the testing process.
Established a framework suitable for undergraduate education and future RISC-V designs.

Abstract

The emergence of open-source Instruction Set Architectures (ISAs) has positioned RISC-V as a key enabler in modern VLSI system design. This paper presents the architectural design, Verilog HDL implementation, and cycle-accurate functional verification of a 32-bit single-cycle processor core compliant with the RV32I base specification. The proposed core integrates an Instruction Fetch Unit (IFU), arithmetic logic unit (ALU), register file, and a dedicated data memory module, referred to as the Warehouse, in a textbook single-cycle datapath suitable for teaching and FPGA prototyping. Functional correctness is validated using a Fibonacci benchmark program assembled for RV32I, with simulation executed on the Xilinx Vivado toolchain. A TCL-based automation flow performs a full-state dump of the final program counter, complete register file contents, key control signals, and Warehouse memory state, and correlates them with the expected Fibonacci sequence. Complementary waveform analysis of the program counter, ALU, register file, and memory interfaces confirms that all state updates occur on the active clock edge and that control flow follows the intended loop structure. The results demonstrate correct instruction execution, stable control flow, and reliable memory operations, establishing a reusable platform for undergraduate education and as a foundation for future pipelined and ASIC-oriented RISC-V designs.

Ask AI

Helpful

Bookmark

View Full Paper