Hardware-Efficient Real-Valued Neural Predistorter for Multimode Power Amplifiers

Digital predistortion (DPD) is essential for mitigating nonlinear distortion in radio-frequency (RF) power amplifiers (PAs), particularly in modern multimode transmitters. Among the existing approaches, the neural-network-based DPD reference model adopted in this work is attractive due to its high modeling accuracy and effective predistortion capability. However, its practical implementation is hindered by the computational complexity of the preprocessing stage, which relies on magnitude extraction, phase normalization, and trigonometric operations. Motivated by this limitation, this work proposes a simplified hardware-efficient formulation, derived from an existing real-valued three-layer perceptron (TLP)-based DPD model, for multimode PA linearization. The proposed approach preserves the main characteristics of the reference model while replacing conventional magnitude and phase normalization with a simplified feature representation derived from complex-valued signal products, eliminating square-root, reciprocal, and trigonometric operations. Two configurations are investigated: a single-network formulation and an iterative cascaded structure composed of compact networks trained sequentially. Simulation results demonstrate accuracy comparable to the reference model while reducing computational complexity by up to 34% in multiplications, 25% in additions, and 73.9% in LUT usage, making the proposed approach suitable for FPGA and ASIC implementations.