Combinatorial optimization problems (COPs) are challenging for conventional computers because their solution spaces grow exponentially. To reduce exhaustive-search burden, hardware approaches have explored stochastic traversal of energy landscapes, including quantum annealers, CMOS Ising solvers, and probabilistic computing systems. However, quantum annealers require cryogenic operation, while CMOS Ising solvers typically rely on pseudorandom bitstreams or shared random pulses. A CMOS-compatible probabilistic bit with a physical random source is attractive for scalable optimization hardware. We present a CMOS p-bit that generates stochastic states from transistor device noise. The p-bit combines a transistor-noise random source, a correlated double sampling circuit, a calibrated comparator, and a 5-bit probability controller to convert local-field inputs into digitally tunable output probabilities. Because the random source is local to each p-bit and does not require PRNG state or seed assignment, the local random-source circuit in each p-bit does not need to grow larger as the number of p-bits increases, while system-level scaling is still governed by the p-bit count, weighted-sum logic, and interconnects. Prototype p-bit chips fabricated in a 180 nm CMOS process show 32-level output-probability control, pass the NIST Statistical Test Suite, and achieve 50 MHz updates with 6.95 pJ/bit at 50% output probability under a 1.8 V supply. Interfaced with FPGA-based weighted-sum logic, the prototype probabilistic circuit demonstrates invertible Boolean operation using a clamped gate network and performs integer factorization.
Jeon et al. (Sun,) studied this question.