Ensuring functional correctness in digital circuitry is arguably the most labor-intensive stage of hardware creation, routinely accounting for upwards of 70% of a project’s total resource allocation. While traditional coverage-driven verification (CDV) attempts to validate every operational state, reaching full coverage closure via manual intervention or constrained–random techniques requires significant engineering time and domain knowledge. To overcome this bottleneck, this study introduces an automated testing architecture that leverages the Advantage Actor–Critic (A2C) Reinforcement Learning (RL) algorithm. This agent intelligently navigates functional coverage closure across five diverse hardware designs: an Advanced Peripheral Bus Universal Asynchronous Receiver-Transmitter (APB UART), an Serial Peripheral Interface (SPI) Memory unit, a synchronous First-In First-Out (FIFO) queue, an APB RAM, and an Advanced High-performance Bus (AHB) Slave interface. By interfacing QuestaSim 2024.1 with a Python-based intelligent agent via a SystemVerilog DPI-C socket, the system dynamically produces test vectors informed by real-time coverage metrics. Based on evaluations across five distinct random seeds, the methodology successfully attains 95.1% to 100% coverage across all testbenches, with three designs achieving 100% and two reaching 95–98%. Notably, the RL-guided system achieved target coverage using approximately 35% fewer simulation cycles than an unguided random baseline, and 22% fewer cycles compared to a traditional constrained–random setup utilizing expert-defined rules. Ultimately, this framework bypasses the necessity for manual constraint formulation and seamlessly scales to novel hardware environments with negligible setup overhead.
Krishnappa et al. (Wed,) studied this question.