In modern high-performance chip design, achieving timing closure is essential to design success. With the increasing scale and complexity of modern chips, timing-driven placement has become increasingly important. Traditional placement methods primarily focus on minimizing wirelength, but lack timing optimization, making it difficult to meet the strict timing closure requirements of modern designs. Therefore, developing an efficient timing-driven placement method has become a critical challenge in modern chip design. This paper presents a novel timing-driven placement framework that integrates a variational graph autoencoder (VGAE) with a nonlinear mixed-size placement optimizer. The framework identifies timing-violation paths through static timing analysis and dynamically adjusts interconnect weights based on pin-level timing slack, enabling the VGAE to generate an initial placement that prioritizes critical-path optimization. Experimental results on the ICCAD2015 benchmarks show that the proposed method achieves a 25.4% improvement in worst negative slack and a 18.1% improvement in total negative slack compared with DREAMPlace4.0. These results demonstrate its effectiveness in improving timing quality.
Ju et al. (Thu,) studied this question.