Division (DIV), reciprocal (REC), square root (SR), and reciprocal square root (RSR) are fundamental operations in digital signal processing (DSP), communication, and matrix decomposition applications. However, implementing these functions using dedicated hardware units increases area and resource utilization when multiple operations are required within the same system. This paper presents a multifunctional fixed-point architecture that supports DIV, REC, SR, and RSR operations within a unified Newton–Raphson-based framework. The proposed design employs scaling and de-scaling techniques to facilitate architectural parameterization across generic fixed-point formats, piecewise polynomial approximations for seed generation, and hardware sharing between the seed computation and Newton–Raphson stages to enhance overall computational efficiency. The architecture was described in Verilog–HDL and evaluated through FPGA and ASIC implementation flows. To demonstrate the feasibility of the design, the experimental validation and implementation scope were focused on a specific of 16 bits word-length. FPGA synthesis results show that the proposed multifunctional unit achieves operating frequencies comparable to dedicated implementations while reducing hardware cost by approximately 40% compared with separate arithmetic units. Exhaustive simulations using a 16-bits representation yield SQNR values ranging from 72.03 dB to 81.03 dB across the supported operations. Furthermore, ASIC implementation using an Intel 16 nm PDK confirms the feasibility of the proposed approach for advanced technology nodes under the verified format. These results demonstrate that the proposed architecture provides an effective trade-off among accuracy, latency, and hardware efficiency, making it well suited for high-performance fixed-point DSP accelerators.
Gutiérrez-Ramos et al. (Thu,) studied this question.