A Metric for Dense Packing and ALU Reinterpretation

This research presents a formal framework for executing ternary (base-3) arithmetic directly on standard binary hardware without modifying the core Arithmetic Logic Unit(ALU). By exploiting the Diophantine approximation of the irrational constant log base 2 of 3, optimal integer pairs for packing ternary digits into binary words are derived, such as five ternary digits into eight binary bits, seventeen into twenty-seven, twenty-nine into forty-six, and forty-one into sixty-five. These packings achieve state utilization efficiencies exceeding ninety-eight percent, approaching the Shannon information limit. It's proven mathematically that standard binary addition and multiplication on these packed integers natively perform the correct ternary carry propagation up to the maximum representable limit of the ternary word. The binary carry chain automatically handles base-3 carries without requiring any changes to the adder circuitry. The only hardware modification necessary is a threshold comparator for overflow detection, which adds fewer than fifty transistors for an eight-bit datapath, representing a negligible area overhead. Among the derived packings, the forty-one-into-sixty-five packing is identified as the engineering favoured, providing a floating-point dynamic range exceeding binary double-precision by several orders of magnitude while fitting neatly into a sixty-four-bit memory bus. The unused binary states, traditionally viewed as waste, are repurposed as an in-band control plane for overflow, infinity, and compression markers, similar to IEEE 754 reserved patterns. This work offers a practical, low-cost bridge to harness the theoretical radix economy of base-3 on existing silicon, bypassing the physical challenges of multi-level voltage logic entirely. The framework is applicable to memory-constrained embedded systems, machine learning inference, and cryptographic acceleration, where dense packing and dynamic range are critical.