Monolithic three-dimensional integration enables dense vertical stacking of devices with fine-pitch interconnects, offering a promising route toward high-density, energy-efficient logic and memory systems. However, its implementation is constrained by the thermal budget of back-end-of-line processes, which must remain below 400 °C to avoid degrading underlying circuitry. While various low-temperature semiconductors have been explored, current demonstrations remain confined to fixed stacking sequences due to high-temperature growth or transfer requirements. Here, we demonstrate a M3D complementary field-effect transistor architecture using low-temperature-deposited n-type In2O3 and p-type Te semiconductors. This platform resolves existing thermal constraints, demonstrating the design freedom to reverse n- and p-type sequences. This capability enables the integration of CMOS inverters, multilayer logic stacks, and a fully functional 3D SRAM storage cell, all fabricated below 300 °C. This scalable platform provides a practical pathway for constructing vertically integrated complementary logic with intrinsic interconnects, paving the way for next-generation 3D system-on-chip technologies. Monolithic 3D integration employs low-temperature n-type In2O3 and p-type Te semiconductors, enabling reversible stacking of complementary field-effect transistors. This method maintains fabrication below 300 °C, facilitating efficient logic and memory circuit development for advanced applications.
Weng et al. (Thu,) studied this question.