What type of study is this?

This is a Experimental Study study.

September 20, 2025

The Graph’s Apprentice: Teaching an LLM Low-Level Knowledge for Circuit Quality Estimation

Key Points

The proposed model enhances circuit quality estimation, outperforming graph-based techniques on benchmark datasets.
Performance comparisons illustrate that utilizing graph neural networks leads to better estimates than current methods.
This work integrates predictor networks within LLMs, enabling real-time feedback on HDL code quality for designers.
Embedding lower-level circuit insights into the model improves accuracy, benefiting the overall circuit design process.

Abstract

Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditional logic synthesis methods are computationally intensive, restricting their iterative use in refining chip designs. Recent advancements in large language models (LLMs), particularly those fine-tuned on programming languages, present a promising alternative. This work proposes augmenting LLMs with predictor networks trained to estimate circuit quality directly from HDL code. To enhance performance, the model is regularized using embeddings from graph neural networks (GNNs) trained on Look-Up Table (LUT) graphs, thereby incorporating lower-level circuit insights. The proposed method demonstrates superior performance compared to existing graph-based RTL-level estimation techniques on the established benchmark OpenABCD, while providing instant feedback on HDL code quality.

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