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This is a Quantitative Study study (also classified as: Experimental Study).

October 2, 2025

Analysis, Simulation and Design of Ternary Logic Circuits Based on CNTFETs in Verilog‐A

Key Points

CNTFET-based ternary logic gates achieved an approximately 80% reduction in delay times.
The proposed design allows for easier evaluation of propagation delay compared to existing methods.
All simulations were conducted in Verilog-A, streamlining the design process.
Ternary logic circuits hold promise for enhancing circuit complexity and power efficiency.

Abstract

ABSTRACT The field of portable electronics and smart devices has seen a significant shift toward multi‐valued logic (MVL), especially ternary logic, due to its potential to reduce circuit complexity and power consumption. This paper shows how Carbon Nanotubes FETs (CNTFETs) can be used in the design of ternary logic gates, which is a promising alternative to the conventional binary logic design. In particular, we propose a procedure to design CNTFET‐based NOR/NAND gates and a Decoder, all in ternary logic, and the proposed method allows us to evaluate the propagation delay. Comparing the proposed design with the existing design, the delay times are reduced by approximately 80%. Moreover, the main novelty is that in this paper all simulations are performed in Verilog‐A, thus avoiding the problems presented in SPICE. The obtained results are encouraging and demonstrate that CNTFET‐based ternary logic gates can be a viable approach for the design of low‐power, high‐speed circuits.

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Analysis, Simulation and Design of Ternary Logic Circuits Based on CNTFETs in Verilog‐A

Key Points

Abstract

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