Quest for More Moore at the End of Device Downsizing

It is anticipated that the downsizing of the CMOS device will end soon, but Moore’s law will continue for several more generations. In recent technology nodes, the performance improvement and higher density of CMOS integrated circuits depended on the smaller footprint resulting from a larger fin height of FinFETs. As device scaling approaches its end, every possible method to increase chip density has been extensively explored. These include the introduction of nanosheet or forksheet structures, better arrangement of power rails and three-dimensional stacking technologies from the device level to the system level. In this review, we highlight various strategies for extending Moore’s law. We discuss the challenges of nanosheet transistors, which are believed to be the ultimate MOS structure and will be implemented in the next technology node. We also discuss some alternative ultimate MOS structures. Nevertheless, from the technological and economic points of view, the mainstream technology in the coming decades should be 3D stacking technology such as CFET at the device level and monolithic 3D technology for system integration.