Convolutional neural networks have become the foundation of image-inference tasks, with systolic array architectures providing enhanced computational performance and efficiency. However, the numerous processing elements (PEs) involved introduces significant challenges in terms of hardware overhead and reliability, which typically exhibit a trade-off relationship. Enhancing the efficiency and reliability of individual PEs can effectively address these challenges and substantially improve the overall performance of systolic array systems. We propose a module that can be implemented in PEs by integrating local binary patterns and min-max operations to reduce both power consumption and hardware size. This approach reutilizes the optimized architecture for fault detection, thus effectively minimizing the testing overhead. Our method enhances the overall system reliability by implementing a fault-PE bypass mechanism, thereby ensuring a robust operation. Experimental results show that the proposed module reduces the hardware area by 29.03% compared with previous circuits when synthesized with the Nan Gate 45 nm library. Furthermore, its dynamic power consumption is 13.72% lower compared with that of existing circuits when implemented on a field-programmable gate array. The results of a fault-injection experiment show that the proposed module reduces errors by up to 33.57% compared with previous circuits and that its test coverage exceeds 94%, with stuck-at 1 faults on PE input registers.
Yoon et al. (Fri,) studied this question.