Semiconductor manufacturing involves numerous process steps, requiring highly precise techniques that are costly and time‐consuming. Therefore, artificial intelligence (AI) is widely utilized to enhance production efficiency and optimize yield, which is directly related to cost. Among the AI techniques, nonlinear variation decomposition (NLVD) quantitatively evaluates the contribution of each input variable to the output for individual samples. However, conventional NLVD methodology is limited to analyzing sample‐level data on a wafer, and the interdependence among contributions from each input complicates direct application to variance decomposition at the LOT level, which represents a bundle of wafers (WFs). This study proposes a novel approach, combining NLVD with statistical techniques to quantify contributions of each unit process to device/circuit performance and variance at the LOT level. To ensure reliable evaluation, the introduced WF‐mean sampling enhanced model performance, increasing the average by 2.5% compared to random sampling. Comprehensive validation is performed, and analysis of the contribution of each unit process to the variance of the figure of merit shows an average error reduction of 85.5% relative to the conventional error propagation law. The proposed methodology enables precise calculation of performance/variance contributions to identify unit processes for yield improvement in semiconductor LOTs, thereby enhancing yield management.
Kang et al. (Fri,) studied this question.