Thermal reliability of two-dimensional (2D) material-integrated complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) has emerged as a critical bottleneck restricting its industrial deployment. Thermally induced stress can cause cracking or buckling of the top-layer 2D materials. It ultimately leads to performance degradation or failure of the ICs. This work investigates the thermal management of graphene-integrated structures under complex operating conditions. It covers both direct and indirect integration schemes, including varied surface integration architectures, vertical interconnect integration, pulsed laser irradiation, and dynamic logic switching operations. The thermo-mechanical performance of graphene is further against black phosphorus (BP) and molybdenum disulfide (MoS 2 ) integrated with CMOS ICs. The results demonstrate that the structural complexity of the surface integration scheme governs the thermal reliability of the top-layer 2D material. Graphene outperforms BP and MoS 2 in both interfacial reliability and thermal transport performance. The introduction of vertical metal interconnects (MVIs) increases the maximum interfacial deformation amplitude of the graphene model from 20.896 nm to 27.016 nm, and alters the distribution of interfacial stress. Under dynamic logic operations, a 4-element pixel array (Array-4) exhibits a maximum temperature difference of 37 K and a maximum interfacial deformation amplitude difference of 20 nm under different logical operating modes. This study provides theoretical and design guidance for thermal reliability optimization of 2D material-CMOS integrated systems, and facilitates the commercialization of 2D materials in large-scale integrated circuits. • The research fills the research gap of thermomechanical reliability under dynamic and complex conditions in the 2D material integrated with silicon-based CMOS integrated systems. • The synergistic coupling effects of surface structure design, 2D material selection, metal interconnection distribution and dynamic conditions on heat conduction / stress-strain are systematically quantified. • Based on the calibration of industrial CMOS back-end process parameters, the research results are used to guide the reliability design of highly integrated ICs and optoelectronic devices. It is expected to meet the actual needs of large-scale application of 2D materials in the semiconductor industry.
Huang et al. (Thu,) studied this question.