As the scaling of conventional SRAM faces fundamental physical and area limitations, novel device architectures are essential for next-generation computing. This paper proposes and comprehensively evaluates a novel 3-Tier 6T-SRAM cell based on a vertically stacked Complementary FET (CFET) architecture that incorporates 2D Transition Metal Dichalcogenides (TMDs) as channel materials. The proposed 3-Tier CFET architecture demonstrates a significant cell area reduction of approximately 29. 5% compared with the Conventional 2-Tier structure. This miniaturization lowers the internal-node capacitance by 13–22%, yielding markedly better write performance (e. g. >39% lower write energy). By systematically adjusting the nanosheet stack ratios (PU: PD: PG), we precisely control the trade-offs between stability and speed. The optimized design (2P4N + 3NAccess) improves read-access time by 11. 9% while maintaining robust write characteristics. This synergistic optimization results in a 24. 9% reduction in the Energy-Delay Product (EDP), indicating improved overall efficiency. These findings validate that the strategic integration of a 3-Tier CFET architecture with 2D TMDs channels provides a robust pathway to high-density, high-performance, energy-efficient SRAM for future high-performance computing and low-power mobile application.
Lee et al. (Fri,) studied this question.