High performance Si-MoS2 heterogeneous embedded DRAM

Embedded Dynamic RAM (eDRAM) has become a key solution for large-capacity cache in high-performance processors. A heterogeneous two transistor capacitorless eDRAM (2T-eDRAM) that combines silicon and molybdenum disulfide (MoS2) is reported to address the short retention issue in conventional gain cell (GC) eDRAMs meanwhile eliminate the pillar capacitor in one transistor and one capacitor (1T1C) eDRAMs. The MoS2 write transistor with low OFF current (IOFF) enables long data retention, while the Si read transistor offers high drive current and logic compatibility. This combination enhances data retention by 1000 times and sense margin by 100 times respectively compared to full Si and MoS2 counterparts. A three-dimensional (3D) design stacking MoS2 on Si is demonstrated with back-end-of-line (BEOL) process to double integration density. With 6000 s data retention, 35 μA/μm sense margin, 5 ns access speeds, 3D integration and CMOS logic compatibility, this Si-MoS2 eDRAM marks a significant advancement in memory technology. This work reports a heterogeneous two transistor capacitorless eDRAM combining Si and MoS2 to solve the short data retention problem while preserving a high sense margin. The retention and sense margin show improvements of 1000 and 100 times respectively compared to full Si and MoS2 counterparts.