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Nonvolatile-memory-based computing in memory (nvCIM) 1–6 is ideal for low-power edge-Al devices requiring neural network (NN) parameter storage in the power-off mode, a rapid response to device wake-up, and high energy efficiency for MAC operations (EF₌₀₂). Current analog nvCIMs impose a tradeoff between the signal margin (SM) and the number of accumulations (N₀₂ₔ) per cycle versus EF₌₀₂ and computing latency (T₂₃-₌₀₂). Near-memory computing (NMC), with high precision for inputs (IN), weights (W), and outputs (OUT), and a high N₀₂ₔ is a trend to improve EF₌₀₂, T₂₃-₌₀₂, and accuracy. A prior STT-MRAM NMC 1 uses vertical-weight mapping (VWM) to improve the EF₌₀₂ ; however, further improvement is challenging: due to (1) the large energy consumption in reading repetitious weight data across multiple inputs for a single NN-layer; (2) a high bitstream toggling-rate (BTR) for digital MAC circuits (DC₌₀₂) reduces EF₌₀₂, and; (3) a limited SM and memory readout latency (T₂₃-₌) for memories with a small R-ratio (e. g. STT-MRAM, see Fig. 33. 2. 1). In developing an STT-MRAM nvCIM macro, this work moves beyond circuit-level novelty by using system-software-circuit co-design. This work achieves a high EF₌₀₂, a short T₂₃-₌, a high read bandwidth (R-BW), a high IN-W-OUT precision, and a high N₀₂ₔ by using the novel schemes: (1) a hardware based weight-feature aware read (WFAR) to reduce weight accesses and improve EF₌₀₂ with a minimal area overhead; (2) toggling-aware weight-tuning (TAWT) to obtain fine-tuned weights (W₅ₓ) with a low BTR, which is based on VWM to enhance the EF₌₀₂ of the DC₌₀₂ ; (3) a differential charge-accumulating margin-enhanced voltage-sensing amplifier (DCME-VSA) to enhance the SM, while reducing the T CD - M. The proposed 22-nm S-Mb STT-MRAM NMC nvCIM macro achieves the highest R-BW (436GB/s) and EF₌₀₂ (46. 4-160. 1TOPS/W) for N₀₂ₔ=576 for SblN - SbW - 26bOUT.
Chiu et al. (Sun,) studied this question.