The advancement of readout integrated circuits (ROICs) with sub-5μm pixel pitch represents a pivotal technological foundation for developing next-generation large-format infrared focal plane arrays (IRFPAs). As short-wave infrared (SWIR) detectors increasingly target ultra-miniaturized pixel configurations down to 5μm dimensions, the integration of high-performance digital ROICs with on-chip analog-to-digital converters (ADCs) has become critical to achieving system miniaturization and enhanced functionality. This study addresses the dual challenges of ultra-fine-pixel circuit design and high-density digital integration through these key advancements: an optimized capacitive transimpedance amplifier (CTIA)-based pixel architecture utilizing single-ended common-source operational amplifiers in 0.18μm CMOS technology, enabling robust 5μm-pitch implementation; a column-parallel dual-ramp two-step single-slope ADC architecture with significantly improved conversion rate compared to traditional structures while overcoming layout density constraints through chip-level resource sharing. Experimental results from a fabricated 640×512 InGaAs digital ROIC prototype validate full functionality with 90kS/s conversion rate and 11.12-bit effective resolution, achieving output characteristics aligned with theoretical predictions. This research bridges the technological void in core components of infrared focal plane arrays with ultra-fine pitch, delivering a high-density integration solution for next-generation large-format infrared detection systems with substantial engineering merit for aerospace and advanced imaging applications.
Wang et al. (2025) studied this question.