Benchmarking junctionless nanosheet FET and T-shaped nanosheet FETs for sub-5 nm scalable CMOS: digital, analog/RF, and circuit-level insights

Abstract This work for the first time presents a comprehensive performance evaluation of next-generation state-of-art devices such as Junctionless (JL) T-shaped (T) Nanosheet (NS) FET and JL NSFET at sub- 5nm technology node. Both the devices are investigated in terms of digital, analog/RF, linearity, and digital circuit applications using a well-calibrated TCAD setup simulation. A detailed comparison of digital performance metrics reveals that JL-T-NSFET exhibits better performance when compared to JL-NSFET making it well-suited for high-speed logic applications. In analog and RF domains, JL-NSFET exhibits superior intrinsic gain, while JL-T-NSFET delivers enhanced linearity characteristics such as higher VIP2 and IIP3, indicating its potential for low-distortion RF applications and better signal integrity. Circuit-level evaluation through CMOS inverter simulations reveals that JL-T-NSFET achieves higher gain and static noise margin, along with reduced propagation delay making it preferable for high-speed logic circuits. The findings highlight the trade-offs between digital, analog, and RF performance, demonstrating that JL-NSFET is optimized for high-gain analog applications compromising linearity, whereas JL-T-NSFET excels in high-speed digital circuit applications and provides better linearity.