An architecture for three-dimensional integration of dynamic random-access memory that enables higher memory density is presented as a new solution to the bottleneck currently faced in artificial intelligence deployment. The basis of this architecture is a vertical dual-gate two-transistors-zero-capacitor memory cell which yields a small feature size and reliable read operation, and naturally scalable to large-scale arrays. However, three-dimensional integration of the dynamic random-access memory faces highly-limiting challenges related to lateral misalignment and thermal cycling as a result of separate stacking processes. To solve the issues of cell misalignment and thermal cycling, a single step process is used to stack the dual-gate In-Ga-Zn-O transistors simultaneously. By optimizing the contact metallization and its interface through an in-situ ozone oxidation method, the vertical dual-gate transistor exhibits a high on-state current and small subthreshold slope as well as high thermal stability and device variation. Furthermore, a four-bit multi-bit operation is demonstrated with an ultra-scaled 4F2 two-transistors-zero-capacitor dynamic random-access memory to further increase the storage density. The approach presented here provides a promising alternative to high-density three-dimensional dynamic random-access memory integration as a means for more efficient near memory computing for artificial intelligence systems.
Liao et al. (2025) studied this question.