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February 22, 2026Journal of Nanoelectronics and Optoelectronics0 citations

A Low-Power Double-Edge-Triggered Flip-Flop Architecture Employing Cascoded Pull-Up and Pull-Down Transistors

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TAT. AshokRPR. PrabakaranMSM. Saravanan

Key Points

  • This work aims to improve power efficiency and delay in double-edge triggered flip-flops using a novel transistor configuration.
  • Developed a new flip-flop architecture using cascaded pull-up and pull-down MOS transistors.
  • Simulated performance at frequencies of 50 kHz, 100 kHz, and 1 MHz using Tanner SPICE.
  • Analyzed power consumption and Power-Delay Product in comparison to existing designs.
  • Achieved over 95% improvement in Power-Delay Product compared to existing designs.
  • Demonstrated significant reduction in power consumption in low voltage digital circuits.

Abstract

In digital circuits, Double Edge Triggered Flip-Flops (DETFFs) have emerged as a crucial component, specifically in applications that necessitate precision timing. Their flexible design, which allows them to be constructed using a variety of gate logic forms such as Complementary Metal-Oxide-Semiconductor (CMOS) or Transistor–Transistor Logic (TTL), and in multiple configurations including D, JK, and T flip-flops, accentuates their ubiquity in digital circuitry. The present study seeks to augment the current under-standing of static double-edge triggered pulsed flip-flops (DETFFs) and introduces a novel structure. This proposed design incorporates cascaded pull-up and pull-down Metal-Oxide-Semiconductor (MOS) transistors for both the clock and D inputs. We simulated this new configuration at three different frequencies—50 kHz, 100 kHz, and 1 MHz—using Tanner SPICE (TSPICE), operating at a voltage of 1.3 V. Our findings reveal a significantly reduced power consumption by the proposed circuit compared to existing designs. With an improvement exceeding 95% in the Power-Delay Product (PDP), this proposed DETFF emerges as a promising contender for implementation in low voltage, low power digital circuits. The substantial PDP improvement and the power efficiency of our proposed DETFF design underscore its potential in revolutionizing low-power digital circuit design. Thus, this work concentrates on modelling an Energy-Efficient Unequal Cluster Management using the Elephant Herd Optimization approach (EEUCM-EHO) that considers the distance explicitly to reduce energy consumption. The maximal nodes transmission ability is provided with higher significance using the clustering strategy of EHO. Moreover, EEUCM-EHO concentrates on clustering strategies. The anticipated EEUCM-EHO is evaluated with various performance metrics like average energy consumption, network lifetime, average residual energy, and the number of alive nodes.

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Cite This Study

Ashok et al. (2025) studied this question.

synapsesocial.com/papers/699a9d8e482488d673cd3759https://doi.org/10.1166/jno.2025.3828
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Also Consider

Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context:

  1. 1Low-Power Double Edge-Triggered Flip-Flop Circuit Design2008 · 27 citations
  2. 2Analysis of power dissipation in double edge-triggered flip-flops2000 · 51 citations
  3. 3Low power, testable dual edge triggered flip-flops2002 · 50 citations
  4. 4A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops2002 · 52 citations
  5. 5Low power design using double edge triggered flip-flops1994 · 140 citations