Efficient thermal management is essential for high-performance computing and AI chips to prevent overheating and ensure reliable operation. Metallic interlayers, known for their high thermal conductivity and thermomechanical compatibility, facilitate the integration of chips with highly conductive heat spreaders, thereby improving heat dissipation. Accurate characterization of the interfacial thermal resistance (ITR) in such thick chip/heat-spreader substrates is therefore critical for optimizing bonding processes. In this study, we fabricated a heterostructure by bonding a thick Si to a diamond heat spreader via an Au/Au interlayer and extracted the ITR at the buried Au/Au interface. Significantly, we introduce a deeply buried thermal resistance extraction method that harnesses the inherent Au interlayer of Au/Au bonding and a sequential delamination technique to accurately measure the temperature-dependent thermal conductivity and ITR of each interlayer. The proposed method enables accurate quantification of ITR for individual metallic and interfacial layers within Au/Au-bonded heterojunctions—even in thicker device layers and high-thermal-conductivity heat sinks. By resolving layer-specific thermal properties and ITR, this approach facilitates rational optimization of wafer-level metal-bonding processes, unlocking the full thermal management potential of ultrahigh-conductivity substrates like diamond for high-power-density devices.
He et al. (2026) studied this question.