Power-Up Stable DC Offset Cancellation in CMOS Low-Pass Filters Using Mirrored Subthreshold Resistors

This paper presents a three-stage, fifth-order Butterworth active-RC low-pass filter integrated with a power-up stable CMOS DC offset cancellation (DCOC) circuit. The filter achieves a 120 MHz cutoff frequency with a 4-bit programmable gain from 0 to 18 dB. The DCOC circuit, implemented in the final stage, employs mirrored subthresholdresistor- based common-mode feedback sensing to minimize loading on high-impedance nodes. Power-up stability is enhanced by gain-stage-specific enable control. Designed and simulated in the ST 130 nm PD SOI CMOS process, the circuit operates at 1.2 V with an additional 1.8 V supply for the DCOC. The design reduces the 3σ output offset voltage from 200 mV to 1.2 mV at maximum gain, with a start-up settling time of 50 μs. The offset cancellation introduces lower cutoff frequencies of 46 kHz and 11.3 kHz at maximum and minimum gains, respectively. Total power consumption is 21 mW, with an active area of about 590 μm ~ 280 μm. The proposed filter demonstrates effective offset cancellation and reliable power-up stability, making it well suited for high-performance programmable gain applications.