March 3, 20260 citations

High-Speed Low-Power 0.5V 28nm FD-SOI 5T SRAM Cell

Haute-vitesse faible-puissance 0.5V 28nm FD-SOI 5T cellule SRAM

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Analysis evaluates a 5T SRAM cell architecture that achieves high-speed and low-power operation at 0.5V, suggesting enhanced efficiency.

The proposed 5T SRAM cell achieves stable operation with mid-point detection, leading to improved read performance.
Simulation indicates the dynamic bus architecture operates efficiently at 0.5V, enabling speeds of up to 1.2 GHz.
Utilizing a dynamic driver and dummy bus, the design reduces power consumption significantly, with standby currents as low as 1.1 µA.
Highlights the potential for greater efficiency and speed compared to conventional static architectures, emphasizing energy savings.

Khajaahmad Shaik (2016) studied this question.

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March 3, 20260 citations

Haute-vitesse faible-puissance 0.5V 28nm FD-SOI 5T cellule SRAM

Ask AI

Bookmark

Authors

Analysis evaluates a 5T SRAM cell architecture that achieves high-speed and low-power operation at 0.5V, suggesting enhanced efficiency.

The proposed 5T SRAM cell achieves stable operation with mid-point detection, leading to improved read performance.
Simulation indicates the dynamic bus architecture operates efficiently at 0.5V, enabling speeds of up to 1.2 GHz.
Utilizing a dynamic driver and dummy bus, the design reduces power consumption significantly, with standby currents as low as 1.1 µA.
Highlights the potential for greater efficiency and speed compared to conventional static architectures, emphasizing energy savings.