In this paper, a 12-bit, 10 MS/s two-step sub-ranging successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The proposed architecture enables residue amplification within a single-stage SAR ADC by dividing the top-plate sampling node, thereby avoiding the requirement for a multi-stage design. This structure also eliminates gain and offset mismatches between the coarse and fine conversions, enhancing robustness and linearity. Owing to the two-step operation, the total capacitance of the capacitive digital-to-analog converter (CDAC) is reduced by 86% compared to that of a conventional SAR ADC with the same unit-capacitor size. In addition, the residue amplifier drives only one-fourth of the total CDAC capacitance, significantly relaxing its power consumption. A prototype fabricated in a 65 nm CMOS process occupies an area of 252 μm × 227 μm and demonstrates a signal-to-noise and distortion ratio (SNDR) of 65.7 dB at Nyquist-rate input. The total power consumption is 227.7 μW under a 1.2 V supply, resulting in a Walden figure of merit (FoM) of 14.5 fJ/conversion step. These results confirm competitive performance and energy efficiency, even with the use of an analog residue amplifier.
Song et al. (2026) studied this question.