QCA (Quantum Dot Cellular Automata) emerged as potential replacements for CMOS technology in the field of ultralow-power high-density digital circuits. This paper proposed design and development of an area-efficient 2-bit Add-Compare-Select (ACS) unit implemented in QCA for highly computational blocks of Viterbi decoders. The optimized architecture utilizes majority voting logic to tightly couple a 2-bit adder, magnitude comparator, and 2:1 multiplexer in a very small area. Functional verification and performance testing were done in QCADesigner with the Coherence Vector Engine. The simulation results showed that the implementation works correctly and improved upon the equivalent CMOS and earlier QCA implementations with orders of magnitude reduction in energy dissipation and reduced computational latency, thus establishing the proposed ACS unit as a useful building block in the development of future ultra-low-power nanoscale signal-processing and decoding systems.
Kumar et al. (2026) studied this question.