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April 4, 2026ACS Nano2 citations

Scalable Reconfigurable Circuits with Double-Gate MoS 2 Transistors

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KCKuanglei ChenYGYu GengJXJiankun Xiao

Key Points

  • The aim is to develop a scalable and reliable reconfigurable logic unit utilizing double-gate MoS2 transistors.
  • Proposed a logic unit based on double-gate MoS2 transistors (DGFETs).
  • Fabricated a 10 × 10 circuit array demonstrating the largest array in two-dimensional reconfigurable transistors.
  • Achieved four distinct logic functions with an n-type channel through double-gate tuning.
  • Demonstrated XOR/XNOR functions and real-time switching in cascaded circuits.
  • Successfully matched input and output voltage ranges.
  • Showcased full potential of cascading in reconfigurable circuits.
  • Provided practical solutions to previously identified issues in scalability and reliability.

Abstract

Reconfigurable transistors are essential for the development of high-efficiency and high-versatility logic circuits. Present reconfigurable devices primarily achieve more functionality by integrating additional control dimensions which significantly improves area efficiency. However, the reliability issues and fabrication difficulty arising from increased device complexity, along with the critical problem of input/output voltage mismatch, severely limit their cascadability and scalability. Here, we propose a cascadable reconfigurable logic unit based on MoS2 double-gate transistors (DGFETs), which is compatible with conventional integration processes, enabling large-scale fabrication. A 10 × 10 array was successfully demonstrated─representing the largest array to date in the field of two-dimensional reconfigurable transistors for logic. By utilizing double-gate tuning combined with the resistive voltage division mechanism of the inverter, the unit achieves four distinct logic functions using only an n-type channel, while maintaining complete matching of input and output voltage range. Furthermore, we fabricated reconfigurable circuits with XOR/XNOR function through cascaded connections and demonstrated real-time switching between half-subtractor and comparator operations, thereby fully showcasing the unit’s potential of cascading. This work provides a viable and practical approach toward the scalable integration of reconfigurable transistors.

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Cite This Study

Chen et al. (2026) studied this question.

synapsesocial.com/papers/69d0afb4659487ece0fa5bdahttps://doi.org/10.1021/acsnano.6c02873
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