Area-Delay-Power Efficient Carry Select Adder

In Modern VLSI Design, Arithmetic Circuits Are Fundamental Components That Directly Influence The Performance, Power Consumption, And Silicon Area Of Digital Systems. The Carry Select Adder (CSLA) Is One Of The Most Widely Used High-speed Adder Architectures Due To Its Ability To Compute Partial Sums In Parallel For Both Possible Carry Input Conditions. However, The Conventional CSLA Employs Two Complete Ripple Carry Adder (RCA) Units Per Group, Resulting In Significant Area Overhead And Increased Power Dissipation. This Paper Presents A 32-bit Optimized CSLA Architecture That Replaces The Second RCA In Each Group With An Explicitly Hardcoded Gate-level Binary To Excess-1 Converter (BEC) Incorporating Common Boolean Logic (CBL) Optimization. The BEC Module Computes The Increment-by-one Operation Using Shared AND Terms, Eliminating Redundant Logic Operations And Reducing Switching Activity Across The Design. The Proposed Architecture Is Implemented In Verilog HDL And Synthesized On Xilinx Artix-7 FPGA (xc7a100tcsg324-1) Using Vivado Design Suite. Synthesis Results Confirm That The Proposed Design Achieves 14.3% Reduction In Area, 11.1% Reduction In Logic Power, And 6.9% Improvement In Area-Delay Product (ADP) Compared To The Conventional Dual-RCA CSLA, Making It Highly Suitable For Low-power IoT Devices, Embedded Systems, And Battery-operated Portable Electronics.