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April 22, 2026Mathematics0 citationsOpen Access

Time-Reversible Synchronization of Chua Circuits for Edge Intelligent Sensors

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АКАртур КаримовKSKirill ShirninIBI.Yu. Babkin

Key Points

  • To demonstrate time-reversible synchronization in Chua circuits for enhanced performance in edge intelligent sensors.
  • Developed FPGA-based synchronization for analog and digital Chua circuits.
  • Reconstructed dynamical equations and conducted theoretical analysis.
  • Implemented various synchronization algorithms and measured performance against conventional PC synchronization.
  • Achieved complete synchronization at a predefined RMSE of 0.01 with fewer data points than PC synchronization.
  • Reduced detection time of capacitance changes by a mean factor of 4 compared to conventional methods.

Abstract

Time-reversible synchronization (TRS) of nonlinear oscillators is a recently proposed technique that ensures super-exponential convergence of dynamics between master and slave systems, which is beneficial in many real-time applications. Nevertheless, this approach has not been demonstrated in any real-time embedded system to practically verify it and quantitatively estimate its advantages. Furthermore, previous studies did not consider the application of time-reversible synchronization to a wide, practically relevant class of chaotic systems with piecewise-linear nonlinearity. To fill these gaps, in this work, we developed an FPGA-based time-reversible synchronization controller for the analog Chua circuit and its digital counterpart. To achieve complete synchronization, we first reconstructed dynamical equations of the circuit. Then, we performed a rigorous theoretical analysis of synchronization possibility between analog and digital systems by each single variable. Next, we implemented the digital model of the Chua circuit in the MyRIO-1900 FPGA using the reconstructed dynamical model and showed its capability of digital-to-analog and analog-to-digital conventional Pecora–Carroll (PC) synchronization. Then, an algorithm of time-reversible synchronization on MyRIO-1900 was tested, achieving complete synchronization at the predefined normalized RMSE level of 0.01, requiring an average of 8.0 fewer points and a median of 10.1 fewer points than the PC synchronization. Finally, we implemented a proof-of-concept version of a capacitive sensor based on the analog Chua circuit with an FPGA-based observer using PC synchronization or the TRS algorithm with a heuristic selection of a starting point. Our experiments reveal that when using the TRS algorithm, the time needed to detect a pre-selected 3% level of capacitance change is reduced by a mean factor of 4 and a median factor of 4.9 in comparison with the conventional PC synchronization. This allows for using the developed solution in applications where the synchronization rate is crucial, including chaos-based sensing, communication, and monitoring.

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Cite This Study

Каримов et al. (2026) studied this question.

synapsesocial.com/papers/69e866ad6e0dea528ddeb0c7https://doi.org/10.3390/math14081359
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