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April 23, 2026Results in Engineering0 citationsOpen Access

A Low-Power, High-Stability CMOS Bandgap Reference with Post-Regulation for Wearable IoT Applications

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PRPallavi RNKNayana D. KKSK.M. Sudharshan

Key Points

  • The aim is to develop a low-power, high-stability CMOS bandgap reference for wearable IoT devices.
  • Employs analytical design for optimized performance and predictability.
  • Integrates a zero-temperature-coefficient current generator and a temperature-compensated resistor network.
  • Incorporates a post-regulation stage to enhance output accuracy.
  • Achieves a stable voltage reference of 1.2 V with a temperature coefficient of 7.3 ppm/°C.
  • Demonstrates current consumption of only 13.9 µA, significantly reducing power usage.
  • Extends battery life approximately threefold, from 7.25 months to 22 months.

Abstract

Battery-powered wearable IoT devices like fitness trackers and other blue tooth low energy devices used for health monitors, requires an accurate voltage reference circuits with minimal power consumption and higher thermal stability for any PVT variations. However, conventional bandgap reference (BGR) designs have to rely on curvature compensation or trimming techniques to overcome fundamental trade-off between accuracy, power consumption, and circuit complexity. This work presents a low-power, high-stability CMOS bandgap reference employing an analytical design approach for predictable and optimized performance. The proposed architecture integrates a zero-temperature-coefficient (ZTC) current generator with temperature-compensated resistor network to generate constant voltage reference and uses a constant-gₘ bias circuit, as part of dual stage self-timed startup mechanism. The proposed architecture further incorporated with post-regulation stage to enhance output accuracy and power supply rejection. Simulation results show stable voltage reference of 1.2 V with a temperature coefficient of 7.3 ppm/°C over temperature of −40°C to 85°C, with a current consumption of 13.9 µA. The proposed architecture achieves gain over 100dB with phase margin above 70° and PSRR of -42.1dB @ 100kHz with NSD 0.15 nV/√Hz at 1 MHz. The design is analysed analytically and demonstrated using a CR2032 coin cell as a representative case, this indicates that the proposed BGR helps to improve battery lifetime approximately a threefold of its battery lifetime, extending operation from 7.25 months to about 22 months.

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Cite This Study

R et al. (2026) studied this question.

synapsesocial.com/papers/69e9b6aa85696592c86eafa1https://doi.org/10.1016/j.rineng.2026.110629
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