A novel sense amplifier-based flip-flop (SAFF) is proposed for low-power operation. Since setup time is a key timing metric of a flip-flop, SAFF structures with near-zero setup time are advantageous for high-speed applications. However, reducing D-Q delay by increasing transistor size generally increases internal-node switching and power consumption. To address this trade-off, a conditional capture method using a modified NOR gate is proposed. The modified NOR gate compares D and Q and activates the sense amplifier only when required. As a result, unnecessary internal-node switching is reduced, leading to lower power consumption. In addition, unlike conventional conditional precharge sense amplifier-based flip-flop (CPSAFF), the proposed circuit does not require a separate setup time for precharge, which also helps reduce D-Q delay. The proposed circuit was implemented in the gpdk45nm process. Compared with CPSAFF, the proposed circuit achieved C-Q and D-Q delays of 89% and 66%, respectively, and PDPD-Q values of 82%, 78%, and 75% at switching activities of 0.1, 0.5, and 1.0, respectively. These results indicate that the proposed circuit is suitable for low-power mobile applications with long standby periods.
Lee et al. (2026) studied this question.