FPGA-specific accurate and approximate compressor-based multipliers using column restructuring and post-synthesis approximation

Approximate computing reduces computational accuracy to achieve improvements in performance, energy efficiency, and resource utilization. It is well-suited to error-tolerant applications such as image processing and machine learning, where small errors do not substantially affect system behaviour. Since multiplication is a core but resource-intensive operation in these applications, approximate multipliers can greatly reduce hardware cost. Existing designs, however, are largely ASIC-oriented and offer limited benefits on FPGAs due to architectural differences. The complexity of the ASIC design flow and the difference in the underlying fabric often limit the applicability of ASIC-based designs in FPGAs. This paper, therefore, presents accurate and approximate multipliers tailored to FPGA architectures by exploiting their underlying hardware resources, incorporating column restructuring, and applying post-synthesis approximation. The work introduces hardware-efficient 8-bit unsigned multipliers optimized for modern Xilinx (AMD) FPGAs. Our proposed designs focus on exploiting the inherent features of the FPGA fabric to attain optimal/near-optimal mappings. The proposed accurate multiplier uses 45.45% fewer LUTs, 66.6% less power, and achieves an 8.14% reduction in critical path delay compared to the Xilinx LogiCORE IP multiplier. The proposed approximate multiplier further reduces LUT usage by 31.25% as compared to the proposed accurate multiplier, without any significant compromise in the output accuracy. Additionally, compared to previous works, the proposed approximate multiplier requires less hardware, consumes less power, and achieves high accuracy. The efficacy of our proposed approximate multiplier is tested using image processing applications, with promising results.