This work introduces a low-power, linear-in-log capacitance sensing circuit tailored for large-area electrowetting-on-dielectric (EWOD) arrays utilizing thin-film transistor (TFT) technology. By leveraging the intrinsic time constants of the circuit, the proposed approach achieves enhanced sensitivity at low capacitance levels, effectively addressing scenarios where the EWOD electrode capacitance is on par with parasitic capacitances present in the system. Fabricated using a 4. 5~ m Low Temperature Polysilicon (LTPS) TFT process, the circuit demonstrates up to 6-bit resolution, corresponding to 63 distinct measured capacitance levels, and measures capacitance variations as small as 61. 3 fF. Two circuit variants are presented: the first, employing a one-transistor–one-resistor (1T1R) input stage, which operates at a peak/mean power consumption of 16~ W / 3. 0~ W and occupies 324 324~ m2; the second, incorporating a current mirror (CM) input stage, consumes 35~ W / 9. 4~ W with an area of 317 506~ m2. Both implementations mark a significant improvement in resolution, sensitivity and power efficiency compared to the current state-of-the-art in TFT technology.
Lopez et al. (2026) studied this question.