Four-edge type low-density parity-check (FET-LDPC) codes, as an important subclass of multi-edge type LDPC codes, offer greater design flexibility and performance potential due to their heterogeneous edge type structure. However, their multi-dimensional degree distribution significantly increases the complexity of optimization. This paper proposes a joint optimization framework for FET-LDPC codes leveraging the symmetric decoding structure inherent in their dual-branch architecture. The main contributions are as follows. First, an improved decoding model is established to analyze the mutual information transmission among the four edge types during iterative decoding, where the symmetry between the accumulator (ACC) and single parity-check (SPC) branches facilitates balanced information exchange. Second, a full-dimensional extrinsic information transfer (FEXIT) chart suitable for FET-LDPC codes is constructed, capturing the mutual information flow across branches. Third, a collaborative optimization model is designed by integrating the FEXIT chart with multi-constraint linear programming (LP) to perform asymmetric optimization for different edge types. The simulation results show that the proposed method achieves significant performance improvement over unoptimized codes in additive white Gaussian noise (AWGN) channels, particularly at a bit error rate (BER) of 10−6.
You et al. (2026) studied this question.