ABSTRACT A new extremely wideband current‐mode power‐four circuit is presented, incorporating an enhanced current‐squaring stage. A diode‐connected transistor simultaneously biases the squaring and couples the current to the second stage. This configuration allows the biasing voltages of the first and second squaring stages to more effectively reduce nonlinearity and the body effect. Additionally, as a new approach in the proposed circuit, load‐based bandwidth compensation extends the −3 dB frequency of the output current in the gigahertz range. The circuit is implemented using 90‐nm CMOS technology with an input range of , demonstrating reductions in transistor count, complexity, area, and power consumption. It consumes only 58.72 μW and occupies a compact area of 29.5 μm 2 . The −3 dB bandwidth is 21.722 GHz under no‐load conditions and increases to 23.273 GHz with compensation via a resistor load. The output dynamic range is 89.41 dB, with a maximum linearity error of 4.64%. A new method of total harmonic distortion (THD) for near‐zero signals is introduced and used for the presented circuit evaluations. The power supply ( V DD ) and temperature variations, noise analysis, and post‐layout verification confirm the superior performance of the proposed power‐four circuit, especially for implementing exponential function generators and analog multipliers.
Shirazian et al. (2026) studied this question.